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QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: * * * * * * * * * 5V operation Five low noise CMOS level outputs <500ps output skew, Q0-Q4 Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Balanced drive outputs 36mA 80MHz maximum frequency Available in QSOP package QS5935 DESCRIPTION The QS5935 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. Five outputs are available: Q0-Q4. Careful layout and design ensure <500ps skew between the Q0-Q4. The QS5935 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The QS5935 is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. In the QSOP package, the QS5935 clock driver represents the best value in small form factor, high-performance clock management products. FUNCTIONAL BLOCK DIAGRAM PLL_EN /2 CLK_IN PLL FEED BAC K 0 1 Q0 Q1 Q2 Q3 Q4 O E/RST INDUSTRIAL TEMPERATURE RANGE 1 c 2000 Integrated Device Technology, Inc. JULY 2000 DSC-5816/1 QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Rating AVDD, VDD Supply Voltage to Ground DC Input Voltage VIN TSTG Maximum Power Dissipation (TA = 85C) Storage Temperature Range (1) Unit V V W C Max. -0.5 to +7 -0.5 to VDD+0.5 0.5 -65 to +150 GND OE/RST FEEDBACK AVDD VDD AGND CLK_IN VDD GND Q0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q4 N/C GND Q3 VDD Q2 GND PLL_EN GND Q1 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = 25 C, f = 1MHz, VIN = 0V) (1) Pins CIN COUT Typ. 3 4 Max. 4 5 Unit pF pF QSOP TOP VIEW NOTE: 1. Capacitance is characterized but not tested. PIN DESCRIPTION Pin Name CLK_IN FEEDBACK Q0 -Q4 OE/RST PLL_EN VDD AVDD GND AGND I/O I I O I I -- -- -- -- Reference clock input External feedback provides flexibility for different output frequency relationships Clock outputs Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled. When 1, PLL is enabled. When 0, PLL is disabled and the output for Q0 -Q4 will be CLK_IN/2 in frequency. This allows the CLK_IN input to be single-stepped for system debug. Power supply for output buffers Power supply for phase lock loop and other internal circuitries Ground supply for output buffers Ground supply for phase lock loop and other internal circuitries Description 2 QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, AVDD/VDD = 5.0V 10% Symbol VIH VIL VOH VOL VH IOZ IIN Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Hysteresis Output Leakage Current Input Leakage Current Conditions Guaranteed Logic HIGH Level Guaranteed Logic LOW Level IOH = -36mA IOH = -100A VDD = Min., IOL = 36mA VDD = Min., IOL = 100A -- VOUT = VDD or GND, VDD = Max., Outputs Disabled VIN = AVDD or GND, AVDD = Max. Min. 2 -- VDD - 0.75 VDD - 0.2 -- -- -- -- -- Typ. -- -- -- -- -- -- 100 -- -- Max. -- 0.8 -- -- 0.45 0.2 -- 5 5 Unit V V V V V V mV A A POWER SUPPLY CHARACTERISTICS Symbol IDDQ IDD IDDD Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply Current (1) Test Conditions VDD = Max., OE/RST = LOW, CLK_IN = LOW, All outputs unloaded VDD = Max., VIN = 3.4V VDD = Max., CL = 0pF Typ. -- 0.7 -- Max. 1 1.5 0.4 Unit mA mA mA/MHz NOTE: 1. This value is guaranteed but not tested. SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tSKR tSKF tPW tJ tPD tLOCK tPZH tPZL tPHZ tPLZ tR, tF tR, tF FI tPWC DH Parameter (1) Output Skew Between Rising Edges, Q0-Q4 (2,3) Output Skew Between Falling Edges, Q0-Q4 (2,3) Pulse Width, Q0-Q4 Cycle-to-Cycle Jitter (2,5) CLK_IN to Feedback Delay (2,6) CLK_IN to Phase Lock Output Enable Time, OE/RST LOW to HIGH (4) Output Disable Time, OE/RST HIGH to LOW (2,4) Output Rise/Fall Times, 0.2VDD 0.8VDD (2) Maximum Rise/Fall Times, 0.8V to 2V Input Clock Frequency Input Clock Pulse, HIGH or LOW Duty Cycle, CLK_IN (7) (7) Min. -- -- TCYC/2 - 0.4 - 0.15 - 500 -- 0 0 -- -- 10 2 25 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 500 500 TCYC/2 + 0.4 +0.15 +500 10 14 14 2.5 3 80 -- 75 Unit ps ps ns ns ps ms ns ns ns ns MHz ns % NOTES: 1. See Test Loads and Waveforms for test load and termination. 2. This parameter is guaranteed by characterization but not tested. 3. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 4. Measured in open loop mode PLL_EN = 0. 5. Jitter is characterized using an oscilloscope, Q output at 20MHz. Measurement is taken one cycle after jitter. 6. tPD measured at device inputs at 1.5V, Q output at 80MHz. 7. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies. 3 QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS VDD 300 7.0V O UTPU T 100 OUTPUT 300 100 30pF TEST CIRCUIT 1 TEST CIRCUIT 2 1.0ns 1.0ns VDD 0.8VDD 0.5VDD 0.2VDD 0V tPW tR tF 3.0V 2.0V Vth = 1.5V 0.8V 0V TTL INPUT TEST WAVEFORM EN ABLE DISABLE CMOS OUTPUT WAVEFORM 3V 1.5V CONTROL INPU T tPZL OU TPUT N OR MALLY LO W SW ITCH C LO SED 0.5VDD 0.3V tPZH SW ITCH O UTPUT NO R M ALLY HIGH O PEN 0.5VDD tPHZ 0.3V VO H VO L tPLZ 3.5V 0V 0V ENABLE AND DISABLE TIMES TEST CIRCUIT 1 is used for output enable/disable parameters. TEST CIRCUIT 2 is used for all other timing parameters. 4 QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TIMING DIAGRAM CLK_IN tPD FEEDBACK tJ Q tSKF Q0-Q4 NOTES: 1. AC Timing Diagram applies to Q output connected to FEEDBACK . 2. All parameters are measured at 0.5VDD except for tPD, which is measured at 1.5V 5 QS5935 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXXX Device Type X Package X Process Blank Industrial (-40C to +85C) Q Quarter Size Outline Package 5935 Low Skew CMOS PLL Clock Driver with Integrated Loop Filter CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: logichelp@idt.com (408) 654-6459 6 |
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